MATRIX - Maven Academy for Technology, Research, Innovation & eXcellence

Dr Chiranjeevi G N: Experienced VLSI professional and technical trainer with strong expertise in Physical Design, Static Timing Analysis, and Physical Verification. Extensive hands-on experience with industry-standard EDA tools such as Synopsys Design Compiler, PrimeTime, Fusion Compiler, IC Validator, Calibre, and StarRC, and has actively contributed to RTL-to-GDS flow enablement. Successfully delivered multiple industry-aligned training programmes, post-placement support sessions, and advanced technical workshops for graduate engineers and working professionals, focusing on bridging academic concepts with real-world silicon implementation practices.

Involved in curriculum development, mentor coordination, and quality assurance for technical training, ensuring consistent learning outcomes and customer satisfaction. Main strengths include structured problem-solving, technical mentoring, and translating complex VLSI concepts into practical, job-ready skills.

Completed PhD in VLSI Design(ECE) in 2025 Passed out from Jadavpur University in 2013 with M.E. in Electrical Engineering Currently working in Maven Silicon Bangalore as Senior Member Technical Staff My areas of interest & expertise include Verilog HDL, RISC-V,DFT, CMOS VLSI Design, System Verilog, Python Microelectronic Circuits, Digital & Analog Electronic Circuits, Microprocessors & Microcontrollers, Intel 8085, 8086, 8051, Arm Cores, Embedded Systems. Currently associated with Digital RTL Design, RISC-V ISA, DFT and Design Projects(Router, SPI, UART, AMBA) at Maven Silicon I was associated with VLSI Lab (Capgemini VLSI sponsored) and part of the VLSI Research Group of NHCE. Trained in VLSI Design Front End, RISC-V, DFT, Verilog, System Verilog. Languages that I am well versed in include Verilog & Python. and have fundamental knowledge of RISC-V, x85,x86, ARM assembly languages and TCL script. Tools that I am currently working hands on include, Intel Quartus and Xilinx ISE/ Vivado for Verilog models on FPGA. Cadence Xcelium, Questa/Model SIM Fundamental Knowlege of Cadence Genus/ Synopsys DC Silvaco and Cogenda TCAD tools for Device Modelling (TFET | MOSFET). Siemens EDA (Formerly Mentor Graphics) for Schematic, Layout, Synthesis, PD and STA. Additionally, I was the Placement In charge for the students of Electronics & Communication Engineering Department of NHCE, successfully handling the placements of 200+ students every year. Been part of the Multiple Ed-Tech Platforms (Lido Learning, Codingal, Cuemath, ID Tech.) during the Covid- Lockdown, handling online classes for Python, Web, and Game Development. Previously employed by AMC Engineering College, Bangalore, Karnataka from Nov 2020 – Oct2021 Worked as an Assistant Professor in ECE and contributed as a teacher and researcher in VLSI and Embedded System domains. Previously employed by PSIT, Kanpur, UP from Jan 2019 – June 2020 Worked as an Assistant Professor in ECE and contributed as a teacher and researcher in VLSI and Embedded System domains. Previously employed by PITS, Sikar, Rajasthan from Aug 2014 – Jan 2019 Worked as an Assistant Professor in ECE and contributed as a teacher and researcher in VLSI and Embedded System domains. Additionally handled the responsibilities of Controller of Examinations & SPOC (NPTEL Local Chapter). GitHub Profile : https://github.com/Sabitabrata2014 Scopus Profile : https://www.scopus.com/authid/detail.uri?authorId=8952389100

18+ Years of experience in VLSI Design and training, and strong expertise in Verilog, RISC-V architecture, FPGA, GPIO, and AHB-APB protocols. Has

played a key role in developing RTL for RISC-V cores and building self-checking testbenches, while also training hundreds of engineering graduates and professionals in frontend VLSI technologies.  3+ years of experience at Maven Silicon as Senior Member Technical Staff from Mar 2022 till date  5 years of experience at A.J Institute of Engineering and Technology as an Assistant Professor from August 2017 till February 2022.  4 years of experience at St.Joseph Engineering College as an Assistant Professor from October 2013 to August 2017.  6 years of experience at St.Joseph Engineering College as a Lecturer from August 2007 to October 2013.

Experienced Design Verification Engineer with expertise in ARM Cortex-M0

and RISC-V SoC verification, power-aware methodologies, and AMBA bus

protocols. Skilled in building scalable verification environments,

developing reusable testbenches, and driving coverage closure. Strong

background in DSP, scripting automation, and SoC-level verification

strategies with AMBA CHI knowledge. Professional engineer with

experience in design verification. Skilled in using advanced verification

methodologies, debugging, and simulation tools. Strong focus on team

collaboration and delivering reliable results, adaptable to changing project

needs. Known for keen problem-solving abilities and effective

communication with cross-functional teams.

As the Co-founder and Managing Director of Maven Silicon, I lead a top-class VLSI and Embedded training services company that produces over 2000 chip designers every year. I have been in the education industry for more than 20 years, and I am passionate about empowering engineers with the latest skills and technologies in the semiconductor domain. I oversee the business, operations, and technology aspects of Maven Silicon, and I am responsible for creating and executing strategic partnerships with universities and industry players. I have trained over 1000 engineers on various VLSI technologies, such as digital electronics, Verilog HDL, VHDL, and FPGA. I have also helped Maven Silicon expand its market share and emerge as a Centre of Excellence in VLSI. In a successful decade-long journey, we deployed 5000+ VLSI engineers in the Indian semiconductor industry. Before co-founding Maven Silicon, worked extensively as a Teaching Faculty at SirMVIT and VIT.

Dr Chiranjeevi G N: Experienced VLSI professional and technical trainer with strong expertise in Physical Design, Static Timing Analysis, and Physical Verification. Extensive hands-on experience with industry-standard EDA tools such as Synopsys Design Compiler, PrimeTime, Fusion Compiler, IC Validator, Calibre, and StarRC, and has actively contributed to RTL-to-GDS flow enablement. Successfully delivered multiple industry-aligned training programmes, post-placement support sessions, and advanced technical workshops for graduate engineers and working professionals, focusing on bridging academic concepts with real-world silicon implementation practices.

Involved in curriculum development, mentor coordination, and quality assurance for technical training, ensuring consistent learning outcomes and customer satisfaction. Main strengths include structured problem-solving, technical mentoring, and translating complex VLSI concepts into practical, job-ready skills.

Completed PhD in VLSI Design(ECE) in 2025 Passed out from Jadavpur University in 2013 with M.E. in Electrical Engineering Currently working in Maven Silicon Bangalore as Senior Member Technical Staff My areas of interest & expertise include Verilog HDL, RISC-V,DFT, CMOS VLSI Design, System Verilog, Python Microelectronic Circuits, Digital & Analog Electronic Circuits, Microprocessors & Microcontrollers, Intel 8085, 8086, 8051, Arm Cores, Embedded Systems. Currently associated with Digital RTL Design, RISC-V ISA, DFT and Design Projects(Router, SPI, UART, AMBA) at Maven Silicon I was associated with VLSI Lab (Capgemini VLSI sponsored) and part of the VLSI Research Group of NHCE. Trained in VLSI Design Front End, RISC-V, DFT, Verilog, System Verilog. Languages that I am well versed in include Verilog & Python. and have fundamental knowledge of RISC-V, x85,x86, ARM assembly languages and TCL script. Tools that I am currently working hands on include, Intel Quartus and Xilinx ISE/ Vivado for Verilog models on FPGA. Cadence Xcelium, Questa/Model SIM Fundamental Knowlege of Cadence Genus/ Synopsys DC Silvaco and Cogenda TCAD tools for Device Modelling (TFET | MOSFET). Siemens EDA (Formerly Mentor Graphics) for Schematic, Layout, Synthesis, PD and STA. Additionally, I was the Placement In charge for the students of Electronics & Communication Engineering Department of NHCE, successfully handling the placements of 200+ students every year. Been part of the Multiple Ed-Tech Platforms (Lido Learning, Codingal, Cuemath, ID Tech.) during the Covid- Lockdown, handling online classes for Python, Web, and Game Development. Previously employed by AMC Engineering College, Bangalore, Karnataka from Nov 2020 – Oct2021 Worked as an Assistant Professor in ECE and contributed as a teacher and researcher in VLSI and Embedded System domains. Previously employed by PSIT, Kanpur, UP from Jan 2019 – June 2020 Worked as an Assistant Professor in ECE and contributed as a teacher and researcher in VLSI and Embedded System domains. Previously employed by PITS, Sikar, Rajasthan from Aug 2014 – Jan 2019 Worked as an Assistant Professor in ECE and contributed as a teacher and researcher in VLSI and Embedded System domains. Additionally handled the responsibilities of Controller of Examinations & SPOC (NPTEL Local Chapter). GitHub Profile : https://github.com/Sabitabrata2014 Scopus Profile : https://www.scopus.com/authid/detail.uri?authorId=8952389100

Chalam Tirunagari is a Senior Member of Technical Staff with 3.5 years of industry experience, complemented by 6 years of academic experience as an Assistant Professor. He is GATE qualified and holds an M.Tech degree. His technical expertise includes SystemVerilog, UVM, and RISC-V architecture. He specializes in verification of RISC-V designs at both IP and SoC levels, bringing a strong blend of theoretical knowledge and practical verification experience. His background in teaching and industry enables him to approach complex verification challenges with clarity, precision, and a structured methodology.

Ms. Akshaya M. Ganorkar is currently employed as Member Technical staff at Maven Silicon Softech Private Limited in Bengaluru, where she specializes in the VLSI physical design domain and digital design. She holds an M.Tech in VLSI Design from NIT Jaipur. With over five years of administrative and teaching experience at Presidency University, Bengaluru, along with more than one year of technical training at Maven Silicon, she has made significant contributions to both academia and industry. Akshaya has actively participated in various conferences, conducted training sessions, and has published two patents. She is a member of IEEE and serves as a reviewer for several conferences. In recognition of her research contributions, she has been honored with the Protsahan III: Recognition of Research Publications Award.

Hemachandra Bhat has 38 years of experience in the IT industry in Wipro Limited. He has led and developed micro computer systems, System on Chips, embedded systems for robotics applications and AI applications that were deployed in production. He has 3 US patents granted in the area of optical character recognition and robotics. Currently he is working as CTO with Maven Silicon which is a center of excellence in Semicon. He is leading the development and delivery of courses and projects in VLSI and Embedded Systems.

With over 12 years of experience spanning academia, RTL design and verification, and technical training, I have led comprehensive VLSI programs on SystemVerilog, UVM, and advanced verification methodologies, mentoring and upskilling more than 3,000 engineers.

My area of expertise includes ASIC design verification, HDL/HVL development, and UVM-based functional verification across multiple protocols such as AXI, AHB, APB, SPI, and UARTand processor architecture RISC-V

I am working as a Technical Lead at Maven Silicon with expertise in RTL Design and FPGA. Overall 10+ years of experience spanning across Industry and Academia. I have a Masters Degree with a specialization in VLSI and Embedded Systems.